Cyrix III 550 review

The 225 MHz FPU of the Cyrix III is pretty weak when performing multiplies. In Flops 4, which consists of about a 55% mix of multiplication, the Cyrix III is even slower than the Pentium MMX 200, while the Flops 1 test with 63% simple operations (Add and substract) shows that the Cyrix is slightly faster than the P5 MMX core. This might indicate that the Cyrix III's multiplication instruction is not pipelined and has a relatively high latency. Notice that the non-pipelined FPU of the K6-2, which executes multiplies in two clockcycles, is twice as fast as the Cyrix III and the K7-core (350 / 600 MHz) is more than twice as fast clock for clock.

A second-generation Samuel 2 chip will feature an improved floating-point unit, most likely clocked at the same speed as the rest of the core. Samuel 2 will also include 64 KB of exclusive L2-cache, just like the Duron. This core will be manufactured at speeds of 700 and 767 MHz in the first quarter of 2001, reaching 800 and 850 MHz in the second quarter.

While Samuel 2 will offer slightly better single precision / gaming performance than a equivalent K6-2 at the same speed and may even be competitive with the Celeron II (crippled by its slow 66 MHz memory bus), the FPU is not capable of handling double precision floating point work at decent speeds.